Hyde will be signing copies of the book in the Cypress booth and will present on SuperSpeed design on September 10 ... and even Verilog examples for a CPLD plug-on board that enables you to ...

The guys over at hackshed have been busy. [Carl] is making programmable logic design easy with an 8 part CPLD tutorial. (March 2018: Link dead. Try the Wayback Machine.) Programmable logic ...

The application is said to provide CPLD designers with a complete, HDL-centric, modular CPLD design suite. It can be downloaded from the company’s website.

The folks at Lattice Semiconductor have announced the immediate availability of their ispLEVER Classic version 1.2 design tool suite. This tool suite supports all Lattice SPLD, CPLD and select FPGA ...

These characteristics of dynamic and static power can be used to minimize the overall power consumption of a design by compressing required activity into a small time period and turning off the CPLD ...

The ispLEVER Classic design software has been upgraded with the addition of Synopsys Synplify Pro with the HDL Analyst feature set, and an improved ispMACH® 4000ZE CPLD fitter with improved power ...